Default pull-up or pull-down is used, and is part of many chips startup sequence (such as FPGAs and CPUs), to reduce idle/leakage current. With CMOS chips, the input circuit on a pin is often a pair of FETs, one P-channel (upper) and one N-channel (lower) in a classic inverter structure. This draws pico-amps when the input is high or low, holding one transistor on, and the other off. During transition between these states, there is gate current that moves in or out of the input pin, as the gates of these transistors are charged or discharged. This current is transient. During the transition, at about the mid point between ground and VDD (the positive power supply value), both these transistors are in the intermediate condition of not being "hard" on or off. A current flows between the VDD supply and ground while this transition occurs, and this is sometimes referred to as shoot-through current. This current also occurs throughout a CMOS chips internals, on every transition, and is the primary contributor to the current drawn by CMOS chips, and is directly related to transitions per second (often your clock frequency).
Anyway, if you have floating inputs on a CMOS chip, it can float to a level that partially turns on both transistors,
and this shoot-through current will occur for each input pin that has drifted into this region.
Note: while VDD/2 is usually the input level where the effect is worst, an input between maybe 0.3* VDD to 0.7*VDD will have some conduction through both transistors.
Without pull-up or -down, there is nothing to motivate a floating input out of this region. In coin cell low power applications, it is critical that no input pins be left floating.